This invention relates to methods for testing semiconductor circuitry for operability, and to constructions and methods of forming testing apparatus for operability testing of semiconductor circuitry.
This invention grew out of the needs and problems associated with multi-chip modules, although the invention will be applicable in other technologies associated with circuit testing and testing apparatus construction. Considerable advancement has occurred in the last fifty years in electronic development and packaging. Integrated circuit density has and continues to increase at a significant rate. However by the 1980""s, the increase in density in integrated circuitry was not being matched with a corresponding increase in density of the interconnecting circuitry external of circuitry formed within a chip. Many new packaging technologies have emerged, including that of xe2x80x9cmultichip modulexe2x80x9d technology.
In many cases, multichip modules can be fabricated faster and more cheaply than by designing new substrate integrated circuitry. Multichip module technology is advantageous because of the density increase. With increased density comes equivalent improvements in signal propagation speed and overall device weight unmatched by other means. Current multichip module construction typically consists of a printed circuit board substrate to which a series of integrated circuit components are directly adhered.
Many semiconductor chip fabrication methods package individual dies in a protecting, encapsulating material. Electrical connections are made by wire bond or tape to external pin leads adapted for plugging into sockets on a circuit board. However, with multichip module constructions, non-encapsulated chips or dies are secured to a substrate, a typically using adhesive, and have outwardly exposed bonding pads. Wire or other bonding is then made between the bonding pads on the unpackaged chips and electrical leads on the substrate.
Much of the integrity/reliability testing of multichip module dies is not conducted until the chip is substantially complete in its construction. Considerable reliability testing must be conducted prior to shipment. In one aspect, existing technology provides temporary wire bonds to the wire pads on the die for performing the various required tests. However, this is a low-volume operation and further requires the test bond wire to ultimately be removed. This can lead to irreparable damage, thus effectively destroying the chip.
Another prior art test technique uses a series of pointed probes which are aligned to physically engage the various bonding pads on a chip. One probe is provided for engaging each bonding pad for providing a desired electrical connection. One drawback with such testing is that the pins undesirably on occasion penetrate completely through the bonding pads, or scratch the bonding pads possibly leading to chip ruin.
It would be desirable to overcome these and other drawbacks associated with testing semiconductor circuitry for operability.